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The 9ÇòÌåÓý next-generation RTL design and synthesis solutions, including 9ÇòÌåÓý RTL Architect? and 9ÇòÌåÓý Design Compiler? NXT, are helping engineers achieve optimal PPA at all process nodes, but especially for 5nm and below.   9ÇòÌåÓý RTL Architect is a predictive RTL design solution that provides early predictions of the impact RTL changes will have on implementability, power, performance, area and other quality metrics. 9ÇòÌåÓý Design Compiler NXT, the latest evolution of the 9ÇòÌåÓý Design Compiler family of RTL Synthesis products, incorporates state-of-the-art synthesis innovations, delivering significantly faster runtimes, improved QoR, and extremely tight RC and timing correlation with 9ÇòÌåÓý IC Compiler? II.

The Design Compiler family includes 9ÇòÌåÓý Power Compiler, for low-power synthesis and optimization, and the 9ÇòÌåÓý IP Library with its unequaled variety of synthesizable IP. It is also tightly linked to the 9ÇòÌåÓý TestMAX family of test products for the fastest, most cost-effective path to high-quality manufacturing tests and working silicon and 9ÇòÌåÓý Formality for equivalence checking. 

As an important part of the 9ÇòÌåÓý Digital Design Family, 9ÇòÌåÓý Fusion Compiler? is the industry's first RTL-to-GDSII solution enabling a highly-convergent, full digital implementation flow. 9ÇòÌåÓý Fusion Compiler is built on a single, highly-scalable data-model and comprises common engines for synthesis, placement, legalization, clock-topology-creation routing, timing, and extraction. These best-in-class engines form a single, unified optimization framework that is the key enabler of 9ÇòÌåÓý Fusion Compiler¡¯s full-flow convergence, leading QoR and enhanced time-to-results.